This task covers the development of a new Front End Module in 65RFSOI technology. It will address the architecture partitioning taking into account not only the performance but also the scalability, power consumption and cost of the overall solution. The development will be driven by IMS based on ST 65RFSOI technology, with a first step related to basic IP bloc design and validation on silicon and a second step integrating these IP’s into a full Front End Module supporting NB-IoT/CAT-M radios.
Key steps :
- Delivery of 65RFSOI PDK from WP2
- Tape-out of first RFIC 65RFSOI MPW
- Validation of RFIC block level performance in lab
- Validation of standalone RFIC
- Tape-out of second RFIC 65RFSOI MPW
- Validation of system ready in lab